The invention relates to a semiconductor device, a lead-patterning substrate, and an electronics device, and methods for fabricating the same, and more particularly to a technique which can be usefully applied to joining by gold/tin soldering and an improvement in reliability of the joined portion, in conjunction with joining between external electrodes (bonding pads), arranged on the main plane of a semiconductor chip having an LOC (Lead on chip) structure, and inner leads of a lead-pattern layer on a lead-patterning substrate.
A conventional semiconductor device mounted on a TCP (tape carrier package) type lead-patterning substrate is shown in FIGS. 1A and 1B and FIGS. 2A and 2B. FIGS. 1A and 1B are diagrams showing an example of the semiconductor device for MPU, CPU and the like of four-directional terminals, wherein FIG. 1A is a plan view and FIG. 1B is a cross-sectional view. FIGS. 2A and 2B are diagrams showing the relationship between a lead frame and a semiconductor chip regarding an example of the semiconductor device for IC of a liquid crystal panel, wherein FIG. 2A is a plan view and FIG. 2B is a cross-sectional view. As is apparent from FIGS. 1A and 1B and FIGS. 2A and 2B, TCP 27 has such a structure that a semiconductor chip 1 is connected to a device hole 28 of a TAB (tape automated bonding) tape (a flexible lead-patterning board) 6 through an inner lead 9 and packaged by a molding resin 26.
The TAB tape (flexible lead-patterning substrate) 6 comprises a base film 4, made of a, polyimide resin or the like, a pattern layer 3, an inner lead 9, and an outer lead 8. TCP 27 is mounted on a circuit board 5 through an outer lead 8. In general, an external electrode 2 comprising a salient bump is formed on the semiconductor chip 1 in its main plane. This aims to facilitate the joining between the semiconductor chip 1 and the inner lead 9 and to enhance the reliability of the joined portion. Numeral 7 designates a sprocket hole of the TAB tape 6, and numeral 29 designates a lead terminal on the circuit board 5.
The bump of the external electrode 2 is generally constituted by an about 20 xcexcm-thick electroplating. The inner lead 9 is electrolessly plated with 0.2 to 0.3 xcexcm-thick tin. The tip of the inner lead 9 is generally connected to a pad 2 of the gold bump by means of a high-temperature tool at 500xc2x0 C. This is because the melting point 285xc2x0 C. of a eutectic composition comprising 90% by weight of gold with the balance consisting of tin in an equilibrium diagram for gold and tin is utilized. At a tool temperature of 500xc2x0 C., a reaction layer having a eutectic composition comprising 90% by weight of gold with the balance consisting of tin is thickly grown in the joining interface, realizing strong joining strength.
A tool having a temperature of 500xc2x0 C. is used in order to realize the completion of joining in a short time of about 2 sec. Since the melting point of tin is 232xc2x0 C., joining under conditions of a heating tool temperature of about 240xc2x0 C. and an increase of the joining time to about 10 sec is possible. In this case, however, since the joining is achieved by mutual diffusion between molten tin and gold, the diffusion layer is thin with the joining strength being very low., The solder layer at that temperature comprises 50 to 80% by weight of gold with the balance consisting of tin. In this solder system, therefore, the temperature around 500xc2x0 C. should be set. This temperature is too high for a polyimide film having a Tg of about 300xc2x0 C.
However, protrusion of the inner lead 9 from the device hole and a joining time of about 2 sec permit the polyimide film to withstand without burning. The inner lead 9 is generally prepared by photochemically etching a copper foil and then conducting electroless plating with tin. The number of external electrodes 2 comprising a gold bump in the semiconductor chip 1 is generally about 100 to 500 pins. Joining methods are classified into a method wherein all pins are joined at once in a short time of about 2 sec and a single point bonding method wherein the inner lead 9 is joined one by one in a time of about 0.2 sec/lead.
In the case of single point bonding for 500 pins, a long joining time of about 100 sec is necessary. Therefore, the single point bonding is not extensively used for mass production. The outer lead 8, after bending in the direction of the substrate, is connected to a lead pattern 29 of the circuit board 5 by print reflow of a eutectic solder paste of 63Sn/37Pb or the like.
Gold/tin joining has hitherto been carried out using a eutectic composition (melting point 278xc2x0 C.) having a gold content around 90% by weight. This temperature is a joining temperature posing no problem in an inorganic package, such as a ceramic package. However, it is too high for CSP comprising an organic film material, such as a polyimide. This gold/tin joining technique is disclosed, for example, in Quarterly Journal of the Japan Welding Society, 15 (1), pp. 174 (1997).
The inventors of the invention have examined the prior art technique and have found the following problems.
(1) The temperature of joining between the semiconductor chip 1 and the inner lead 9 is so high that the inner lead 9 should be connected in the state of protrusion from the device hole 28. For this reason, the provision of a device hole 28 is indispensable.
If an external electrode 2 comprising a gold bump in the semiconductor chip 1 is directly abutted against the lead pattern 29 on the base film 4 of polyimide without the formation of a device hole followed by joining while applying a high-temperature tool of 500xc2x0 C., the polyimide resin film would be burned and carbonized, making it impossible to produce a TCP package with good reliability.
This device hole 28 is formed in a polyimide film 4 with an adhesive applied thereto by means of a punching die. The die is expensive, and, in addition, the formation of a hole in the film 4 unfavorably results in lowered tensile strength of the film 4.
(2) As described above, the temperature of the tool for the joining is so high that, when a device hole 28 is formed to form an inner lead 9, the following problem occurs. Due to good thermal conductivity of the inner lead 9 of copper, an increase of the temperature slightly above 500xc2x0 C. for satisfactory joining or a slight prolongation of the joining time causes heat to be conducted through the inner lead, leading to a problem that the polyimide film 9 and the adhesive are burned and carbonized.
The adhesive generally comprises an epoxy resin and has a Tg of about 170xc2x0 C. This has inferior heat resistance to the polyimide and, hence, still has a problem as an adhesive for high-temperature joining. An additional problem is that, when the joining time is shortened in consideration of a problem of damage to the adhesive, a failure of joining occurs making it impossible to provide normal joining strength. Further, designing a joining tool for use at 500xc2x0 C. requires a very high level of technique.
Specifically, in joining at once, the flatness of the joining tool is very important from the viewpoint of a failure of the semiconductor chip 1. However, the influence of the thermal expansion is very large at 500xc2x0 C., and considerable know-how regarding the fabrication is necessary for the maintenance of the flatness at that temperature. When the flatness of the tool is low, uneven stress is applied to the semiconductor chip 1, often leading to a failure of the semiconductor chip 1. In general, a tool flatness of not more than 1 xcexcm is required. In this case, the total cost including the cost of the heating tool and the cost of the stage just under the semiconductor chip 1 is, for example, as high as not less than 1,000,000 yen. This is because heat is transmitted to the stage just under the semiconductor chip 1, rendering the regulation of the flatness of the stage important. Further, the tool temperature used is so high that a design of machine parts in a large sheet thickness and the like are necessary for maintaining the peripheral mechanical accuracy, resulting in increased whole cost of the joining machine.
(3) Flexibility is particularly important for the TAB tape 6. In the prior art technique, however, the film 4 becomes thick because an adhesive is used. Further, since the adhesive per se is a resin, having a high flexural modulus of elasticity, comprising an epoxy resin, a problem of lowered flexibility occurs. In recent years, there is an ever-increasing demand for a reduction in size of domestic electronic appliances, such as portable telephones, leading to a strong demand for a freely bendable TAB tape 6. This low flexibility is a very important issue.
(4) When the device hole 28 is formed to provide an inner lead 9, the base film 4 is not present just under the inner lead 9. Therefore, the inner lead 9 becomes protruded with only one end thereof being supported. In this form of the lead, the tip is very easily bent. This poses a problem of misregistration involved in registration with the external electrode 2 of a gold pad and, in addition, a problem of breaking of leads, and a problem of separation of the semiconductor chip 1 from the joined portion in a period between the completion of the joining and the resin molding attributable to handling associated with transit, resulting in deteriorated reliability.
(5) In conventional semiconductor devices, the guarantee of the reliability in cold districts relies upon a temperature cycling test between xe2x88x9265xc2x0 C. and 150xc2x0 C. In this temperature cycling test, for the conventional structure, the protruded inner lead 9 undergoes tension due to thermal stress. Specifically, the coefficient of thermal expansion of the semiconductor chip 1 is 3 ppm/xc2x0 C., while the coefficient of thermal expansion of the polyimide resin as the base film 4 is 20 ppm/xc2x0 C. Therefore, stress is concentrated on the copper leads interposed between the semiconductor chip and the base film in the temperature cycling test. In general, in the above temperature cycling test, a reliability of about 1000 cycles is required. For this reason, sealing the periphery with a molding resin 26 has been used. However, there is a limit to the performance of the molding resin 26, and small coverage of the molding resin 26 causes breaking of the lead.
(6) In the prior art method, the number of semiconductor chip 1 mounted on one TAB tape is limited to one. This is because the device hole 28 is necessary. Specifically, when a plurality of device holes 28 are formed to mount a plurality of semiconductor chips 1, the strength of the film 4 becomes low. Further, during joining of the plurality of semiconductor chips 1, the leads of the already joined semiconductor chip 1 are disadvantageously broken at the time of handling. Furthermore, an additional problem involved in mounting of the plurality of semiconductor chips 1 is that the cost of the cutting die for the device hole 28 is increased. For this reason, one semiconductor chip should be mounted for each TAB tape. This makes it impossible to produce high-density flexible lead-pattern substrate, such as multi-chip modules.
Therefore, as shown in FIGS. 1A and 1B, TCP 27 is mounted one by one on the circuit board 5. When multi-chip is desired, a plurality of semiconductor chips 1 should be mounted in this form onto the circuit board 5. This results in an increase in the system cost. FIGS. 2A and 2B shows the structure of a TAB tape used in LCD panels. In LCD, on-off driving of transmitted light by backlight of the liquid, crystal panel is carried out by sending a signal from drive IC (semiconductor chip 1). For this, TCP is used in a large quantity. Also in this case, as shown in FIGS. 2A and 2B, the device hole 28 is provided, posing the same problems as descried above.
(7) When a non-sealed semiconductor chip is mounted directly onto a lead-patterning substrate of an organic material without through TCP 27, in general, a eutectic solder of 37 wt % Pb-Sn is extensively used in consideration of the heat resistance of the circuit board 5. The melting point of this eutectic composition is 180xc2x0 C., so that there is no fear of the organic material, such as glass epoxy resin, being damaged. However, the maximum temperature, at which the joined portion can withstand, is so low that the reliability in the above temperature cycling test and a high-temperature (150xc2x0 C.) holding test are disadvantageously low. Further, when the non-sealed semiconductor chip is mounted together with other components, the joined portion cannot withstand the solder paste print reflow mounting temperature, 250xc2x0 C. This causes problems including separation of the non-sealed semiconductor chip.
It is an object of the invention to provide a technique that can improve the reliability with temperature cycling in lead-patterning substrates, semiconductor devices, and electronics devices.
It is another object of the invention to provide a technique that can provide a joining structure with high reliability in lead-patterning substrates, semiconductor devices, and electronics devices.
It is still another object of the invention to a technique that can form at a low temperature a solder layer of a gold/tin solder in joining between a semiconductor chip and inner leads in a semiconductor device.
It is a further object of the invention to provide a technique that can improve the flexibility of a flexible lead-patterning substrate.
It is a still further object of the invention to provide a TAB type flexible lead-patterning substrate that is highly resistant to tension.
A further object of the invention to provide a TAB flexible lead-patterning substrate on which a plurality of semiconductor chips can be mounted.
A still further object of the invention is to provide a chip-size type semiconductor device (CSP type semiconductor device) utilizing a flexible lead layer.
Another object of the invention is to provide a xcexcBGA type semiconductor device having high reliability with respect to temperature cycling.
The above and other objects and novel features of the invention will become apparent from the following description and the accompanying drawings.
According to the invention, the features are summarized as defined below.
(1) A semiconductor device, comprising:
a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion;
an insulating substrate having a predetermined pattern of leads thereon and having no device hole for said semiconductor chip, each of said leads being provided with an inner lead having a joining portion which is joined through solder to a corresponding one of the joining portions of said external electrodes of said semiconductor chip to provide a joined portion; and
a molding resin for sealing said joined portion including the solder,
wherein the joining portion of the external electrode comprises a metal selected from the group consisting of gold and tin;
the joining portion of the inner lead comprises a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion of the inner lead is tin, or vice versa; and
the solder comprises gold/tin solder.
(2) A semiconductor device, comprising:
a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion;
a flexible lead-patterning substrate comprising an insulating, flexible base film having a first plane and a second plane, the first plane having thereon leads each having a joining portion for joining to the semiconductor chip and provided with an inner lead portion electrically connected to the joining portion of said leads, the second plane having therein via holes and joining portions for solder balls, each of the joining portions, for solder balls, being electrically connected through a corresponding one of the via holes to a corresponding one of the inner lead portions and having thereon a solder ball, the external electrodes each in its joining portion being joined through solder to a corresponding one of the joining portions, for the semiconductor chip, provided on the first plane of the base film to form a joined portion; and
a molding resin for sealing said joined portion including the solder,
wherein the joining portion of the external electrode comprises a metal selected from the group consisting of gold and tin;
the joining portion of, for the semiconductor chip, provided on the first plane of the base film comprises a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion provided on the first plane of the base film or is tin, or vice versa; and
the solder comprises gold/tin solder.
(3) A semiconductor device, comprising:
a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion;
a lead-pattering substrate comprising leads provided on an insulating, flexible base film, each of the leads having an inner lead being provided with an inner lead having a joining portion which is joined through solder to a corresponding one of the joining portions of said external electrodes of said semiconductor chip to provide a joined portion;
solder balls electrically connected respectively onto the leads;
a thermal stress cushioning material elastomer for relaxing thermal stress with respect to the semiconductor chip and the leads; and
a molding resin for sealing said joined portion including the solder,
wherein the joining portion of the external electrode comprises a metal selected from the group consisting of gold and tin;
the joining portion of the inner lead comprises a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion of the inner lead is tin, or vice versa; and
the solder comprises gold/tin solder.
(4) The joined portion comprises a solder layer of a gold/tin solder, the solder layer comprising: a fillet which mainly has a composition having. a first eutectic point (melting point 217xc2x0 C.) comprising 5 to 20% by weight of gold with the balance consisting of tin; and a reaction fusion layer (a high melting layer) comprising 20 to 40% by weight of gold with the balance consisting of tin.
(5) The solder layer of gold/tin solder comprise not more than 1.0% by weight of lead as a minor additive element in addition to gold and tin.
(6) The solder layer of gold/tin solder comprises, in addition to gold and tin, a diffusion-dissolved base metal element from the joined metal base.
(7) The joining portion of the external electrode comprises any one of a thick electrolytic gold plating in a bump form, an electroless gold plating, a deposited gold layer, a sputtered gold layer, and a thin gold coating provided on a salient (a bump) of a thick nickel, chromium, copper or other metallic plating.
(8) The joining portion of the inner lead comprises any one of an electrolytic gold plating, an electroless gold plating, a deposited gold layer, and a sputtered gold layer.
(9) The joining portion of the external electrode comprises any one of a thick electrolytic tin plating in a bump form, an electroless tin plating, a deposited tin layer, a sputtered tin layer, and a thin tin plating provided on a thick bump (a bump) of a nickel, chromium, copper or other metallic plating.
(10) The joining portion of the inner lead comprises any one of an electrolytic tin plating, an electroless tin plating, a deposited tin layer, and a sputtered tin layer.
(11) The joining portion of the external electrode comprises a thick sa lien t gold or tin coating, or a gold or tin coating provided on a salient of a metal other than gold or a heat-resistant organic material.
(12) The lead-patterning substrate comprises any one of a copper lead-pattering glass epoxy substrate, a copper lead-patterning glass polyimide substrate, a copper lead-pattering BT resin, a copper lead-patterning fluororesin substrate, a copper lead-patterning aramid substrate, a copper lead-patterning ceramic substrate, a copper lead-patterning (or titanium oxide lead-patterning) glass substrate, a copper lead-patterning polyimide film, a copper lead-patterning liquid crystal polymer, and a copper lead-patterning glass epoxy film.
(13) An electronics device, comprising a Rambus type semiconductor device module, the Rambus type semiconductor device module comprising a plurality of semiconductor devices, according to any one of the above items (1) to (12), mounted on a Rambus type lead-patterning substrate.
(14) A TAB type flexible lead-patterning substrate, comprising a predetermined pattern of leads provided on an insulating, flexible film having no device hole, wherein the lead comprises any one of a rolled oxygen-free foil of copper having a high purity of not less than 99.99% by weight, a high electrolytic copper foil, a deposited copper layer, and an electroless copper plating.
(15) Each of the leads has an inner portion having a joining terminal to be joined to a corresponding one of external electrodes of a semiconductor chip, wherein joining terminal comprises a tin coating, a gold coating provided directly on the joining terminal, or a gold coating provided through a substrate metal.
(16) The insulating, flexible film comprises a liquid crystal polymer.
(17) A method for fabricating a semiconductor device, comprising the steps of:
previously providing a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion comprising a metal selected from the group consisting of gold and tin and a lead-patterning substrate comprising a predetermined pattern of leads provided on an insulating substrate, each of the leads being provided with an inner lead having a joining portion comprising a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion of the inner lead is tin, or vice versa;
conducting registration between the joining portion of each of the external electrodes and the joining portion of a corresponding one of the inner leads;
fixing the semiconductor chip;
heat-pressing the assembly in this state to cause a diffusion reaction of the joining portion of the external electrode with the joining portion of the inner lead to form a joined portion including solder; and
sealing the joined portion including the solder with a molding resin,
wherein, in joining the external electrode to the inner lead, gold or tin constituting the joining portion of the external electrode is brought into intimate contact with tin or gold constituting the joining portion of the inner lead and the assembly is then subjected to joining with heat pressing under conditions of heating temperature 240 to 260xc2x0 C. (first eutectic point: 217xc2x0 C.), applied pressure 1 to 10 kgf/mm2, and heat pressing time 2 to 3 sec to form gold/tin solder as a result of a diffusion reaction.
(18) The joining portion, of the external electrode, comprising gold or tin and the joining portion, of the inner lead comprising tin or gold are formed by electrolytically or electrolessly plating any one of a salient copper and copper, chromium, and nickel layers with gold or tin.
(19) The joining between the semiconductor chip and the lead-patterning substrate is carried out, without providing a device for the semiconductor chip in the lead-patterning substrate, by joining the joining portion of the inner lead to the joining portion of the external electrode of the semiconductor chip by means of a bonding tool.
(20) The semiconductor device is mounted directly as a non-sealed semiconductor chip onto a circuit board, or alternatively is once mounted on an intermediate substrate (an interposer) followed by formation of solder balls.
(21) A method for fabricating a flexible lead-patterning substrate, comprising the steps of:
forming a foil of high-purity copper on a first plane of an insulating, flexible film;
etching the copper foil to form a joining portion for joining to a semiconductor chip and an inner lead portion electrically connected to the joining portion for joining to a semiconductor chip;
forming a via hole in a second plane of the insulating film by means of a laser beam to exposure the backside, comprising the copper foil, of the inner lead portion;
forming an electroless copper plating thereon to form a joining portion, for a solder ball, electrically connected to the inner lead portion through the electroless copper plating on the second plane of the insulating film;
forming a solder ball on the joining portion for a solder ball.
(22) A semiconductor device, comprising:
a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion;
an insulating substrate having a predetermined pattern of leads thereon and having no device hole for said semiconductor chip, each of said leads being provided with an inner lead having a joining portion which is joined through solder to a corresponding one of the joining portions of said external electrodes of said semiconductor chip to provide a joined portion; and
a resin layer, formed from a resin coating or a resin tape, for sealing said joined portion including the solder,
wherein the joining portion of the external electrode comprises a metal selected from the group consisting of gold and tin;
the joining portion of the inner lead comprises a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion of the inner lead is tin, or vice versa; and
the solder comprises gold/tin solder.
(23) The solder layer comprising: a fillet which mainly has a composition having a first eutectic point (melting point 217xc2x0 C.) comprising 5 to 20% by weight of gold with the balance consisting of tin; and a reaction fusion layer (a high melting layer) comprising 10 to 40% by weight of gold with the balance consisting of tin.
(24) A method for fabricating a semiconductor device, comprising the steps of:
previously providing a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion and a lead-patterning substrate comprising a predetermined pattern of leads provided on an insulating substrate having no device hole for semiconductor chip, each of the leads being provided with an inner lead having a joining portion;
forming a resin layer of a resin coating or a resin tape on the inner leads of the leads;
conducting registration between the joining portion of each of the external electrodes and the joining portion of a corresponding one of the inner leads;
fixing the semiconductor chip onto the resin layer; and
heat-pressing the assembly in this state to cause a diffusion reaction of the joining portion of the external electrode with the joining portion of the inner lead to form a joined portion of a solder layer comprising a gold/tin eutectic alloy and, at the same time, melting the resin layer to seal the joined portion including the gold/tin eutectic alloy with the resin.
(25) A gold layer or a tin layer is formed on the joining portion of the external electrode and on the joining portion of the inner lead, provided that, when a gold layer is formed on the joining portion of the external electrode, a tin layer is formed on the joining portion of the inner lead, or vise versa; the gold layer is brought into intimate contact with the tin layer; and the assembly is then subjected to joining with heat pressing under conditions of heating temperature 240 to 260xc2x0 C. (first eutectic point: 217xc2x0 C.), applied pressure 1 to 10 kg/cm2, and heat pressing time 2 to 5 sec to form a solder layer comprising a gold/tin eutectic alloy as a result of a diffusion reaction.